The invention relates to the field of strained silicon surface channel MOSFETs, and in particular to using them in CMOS inverters and other integrated circuits.
The ability to scale CMOS devices to smaller and smaller dimensions has enabled integrated circuit technology to experience continuous performance enhancement. Since the 1970""s, gate lengths have decreased by two orders of magnitude, resulting in a 30% improvement in the price/performance per year. Historically, these gains have been dictated by the advancement of optical photolithography tools and photoresist materials. As CMOS device size progresses deeper and deeper into the sub-micron regime, the associated cost of these new tools and materials can be prohibitive. A state of the art CMOS facility can cost more than 1-2 billion dollars, a daunting figure considering that the lithography equipment is generally only useful for two scaling generations.
In addition to economic constraints, scaling is quickly approaching constraints of device materials and design. Fundamental physical limits such as gate oxide leakage and source/drain extension resistance make continued minimization beyond 0.1 xcexcm difficult if not impossible to maintain. New materials such as high k dielectrics and metal gate electrodes must be introduced in order to sustain the current roadmap until 2005. Beyond 2005, the fate of scaling is unclear.
Since the limits of scaling are well within sight, researchers have actively sought other methods of increasing device performance. One alternative is to make heterostructure FETs in GaAs/AlGaAs in order to take advantage of the high electron mobilities in these materials. However, the high electron mobility in GaAs is partially offset by the low hole mobility, causing a problem for complementary FET architectures. In addition, GaAs devices are usually fabricated with Schottky gates. Schottky diodes have leakage currents that are orders of magnitudes higher than MOS structures. The excess leakage causes an increase in the off-state power consumption that is unacceptable for highly functional circuits. Schottky diodes also lack the self-aligned gate technology enjoyed by MOS structures and thus typically have larger gate-to-source and gate-to-drain resistances. Finally, GaAs processing does not enjoy the same economies of scale that have caused silicon technologies to thrive. As a result, wide-scale production of GaAs circuits would be extremely costly to implement.
The most popular method to increase device speed at a constant gate length is to fabricate devices on silicon-on-insulator (SOI) substrates. In an SOI device, a buried oxide layer prevents the channel from fully depleting. Partially depleted devices offer improvements in the junction area capacitance, the device body effect, and the gate-to-body coupling. In the best-case scenario, these device improvements will result in an 18% enhancement in circuit speed. However, this improved performance comes at a cost. The partially depleted floating body causes an uncontrolled lowering of the threshold voltage, known as the floating body effect. This phenomenon increases the off-state leakage of the transistor and thus offsets some of the potential performance advantages. Circuit designers must extract enhancements through design changes at the architectural level. This redesign can be costly and thus is not economically advantageous for all Si CMOS products. Furthermore, the reduced junction capacitance of SOI devices is less important for high functionality circuits where the interconnect capacitance is dominant. As a result, the enhancement offered by SOI devices is limited in its scope.
Researchers have also investigated the mobility enhancement in strained silicon as a method to improve CMOS performance. To date, efforts have focused on circuits that employ a buried channel device for the PMOS, and a surface channel device for the NMOS. This method provides the maximum mobility enhancement; however, at high fields the buried channel device performance is complex due to the activation of two carrier channels. In addition, monolithic buried and surface channel CMOS fabrication is more complex than bulk silicon processing. This complexity adds to processing costs and reduces the device yield.
In accordance with the invention, the performance of a silicon CMOS inverter by increasing the electron and hole mobilities is enhanced. This enhancement is achieved through surface channel, strained-silicon epitaxy on an engineered SiGe/Si substrate. Both the n-type and p-type channels (NMOS and PMOS) are surface channel, enhancement mode devices. The technique allows inverter performance to be improved at a constant gate length without adding complexity to circuit fabrication or design.
When silicon is placed under tension, the degeneracy of the conduction band splits forcing two valleys to be occupied instead of six. As a result, the in-plane, room temperature electron mobility is dramatically increased, reaching a value as high as 2900 cm2/V-sec in buried channel devices for electrons densities of 1011-1012 cmxe2x88x922. Mobility enhancement can be incorporated into a MOS device through the structure of the invention. In the structure, a compositionally graded buffer layer is used to accommodate the lattice mismatch between a relaxed SiGe film and a Si substrate. By spreading the lattice mismatch over a distance, the graded buffer minimizes the number of dislocations reaching the surface and thus provides a method for growing high-quality relaxed SiGe films on Si. Subsequently, a silicon film below the critical thickness can be grown on the SiGe film. Since the lattice constant of SiGe is larger than that of Si, the Si film is under biaxial tension and thus the carriers exhibit strain-enhanced mobilities.
There are two primary methods of extracting performance enhancement from the increased carrier mobility. First, the frequency of operation can be increased while keeping the power constant. The propagation delay of an inverter is inversely proportional to the carrier mobility. Thus, if the carrier mobility is increased, the propagation delay decreases, causing the overall device speed to increase. This scenario is useful for applications such as desktop computers where the speed is more crucial than the power consumption. Second, the power consumption can be decreased at a constant frequency of operation. When the carrier mobility increases, the gate voltage can be reduced by an inverse fraction while maintaining the same inverter speed. Since power is proportional to the square of the gate voltage, this reduction results in a significant decrease in the power consumption. This situation is most useful for portable applications that operate off of a limited power supply.
Unlike GaAs high mobility technologies, strained silicon devices can be fabricated with standard silicon CMOS processing methods and tools. This compatibility allows for performance enhancement with no additional capital expenditures. The technology is also scalable and thus can be implemented in both long and short channel devices. The physical mechanism behind short channel mobility enhancement is not completely understood; however it has been witnessed and thus can be used to improve device performance. Furthermore, if desired, strained silicon can be incorporated with SOI technology in order to provide ultra-high speed/low power circuits. In summary, since strained silicon technology is similar to bulk silicon technology, it is not exclusive to other enhancement methods. As a result, strained silicon is an excellent technique for CMOS performance improvement.